Semiconductor chips require cooling to sustain reliability of circuits and interconnects formed on and in the semiconductor chips, to optimize circuit switching performance, and to suppress thermally generated noise in the circuits. An increased need for thermal cooling is seen for CMOS transistors, wherein high temperatures yield significantly larger leakage currents due to thermal generation of carriers. Moreover, as device dimensions decrease, leakage current grows exponentially.
As a result, a myriad of cooling structures have been devised for incorporation into the semiconductor chip structure itself and for use with semiconductor chip structures. Cooling may be provided for an entire circuit boards may be applied selectively to individual chips, or may be provided on-chip to dissipate heat from individual hot spots within a chip. Examples of some prior art cooling solutions include U.S. Pat. No. 5,621,616 of A. H. Owens, wherein a high conductivity thermal transfer pathway is created, using multiple metal layers and vias, to draw heat away from the bulk silicon semiconductor substrate. Owens additionally proposes embedding metal plugs into a chip substrate to collect heat generated by transistors and remove the heat through metal interconnects in the chips.
Silicon-on-insulator (SOI) structures for CMOS devices have been developed as an alternative to the bulk silicon device technology for very large scale integration (VLSI) circuits. The SOI structures are preferable due to the advantages provided by the buried oxide (BOX) insulator layer. The BOX advantages include an absence of the reverse body effect, absence of latch-up, soft error immunity, and elimination of the parasitic junction capacitance typically encountered in bulk silicon devices. Reduction of the parasitic capacitance allows for greater circuit density, operation at higher circuit speeds, and reduced power consumption.
FIG. 1 illustrates a typical SOI CMOS structure wherein buried oxide (BOX) layer 103, generally about 0.1–0.5 microns in thickness, is provided in the substrate 101, which comprises 400–600 microns of silicon. For the sake of illustration, silicon-on-oxide (SOI) layer 105 is shown as a p-type silicon substrate having a thickness of about 0.2–1 μm, with an NMOSFET device 104 formed at the surface. Clearly, the ensuing description of both the background and the novel structure and method will be equally applicable to devices formed in an n-type SOI silicon substrate. The NMOSFET device 104, formed in the SOI layer above the buried oxide layer, comprises polysilicon gate 106 and source and drain regions 109. Adjacent NMOSFET devices are both physically and electrically isolated from each other by shallow trench regions 108, typically comprised of an oxide region.
While SOI structures are advantageous for reduction of parasitic capacitance otherwise associated with bulk silicon CMOS devices, there are disadvantages to the isolation provided by the buried oxide layer. With the isolation provided by the buried oxide, the devices cannot dissipate heat to the 400–600 micron silicon substrate, as efficiently as devices formed on bulk silicon had allowed, since the BOX is a thermal barrier.
One structure which has been proposed for SOI cooling is presented in U.S. patent application Ser. No. 08/822,440, entitled “Silicon-On-Insulator Structure for Electrostatic Discharge Protection and Improved Heat Dissipation” which was filed on Mar. 21, 1997 and is assigned to the present assignee. In that application, the contents of which are incorporated by reference herein, thermally conductive plugs are formed passing through the buried oxide region and into the opposite type silicon substrate. The plugs, preferably comprising polysilicon, are in contact with the sources and drains of the CMOS devices to provide paths for dissipating positive and negative ESD stresses, in addition to providing thermal dissipation pathways for directing heat away from the circuitry.
Yet another proposed solution is found in U.S. patent application Ser. No. 09/006,575, of Joshi, et al, entitled “Embedded Thermal Conductors for Semiconductor Chips”, filed on Jan. 13, 1998 and currently under allowance, and its divisional case Ser. No. 09/296,846 filed Apr. 22, 1999, both of which are assigned to the present assignee. In accordance with the teachings of those applications, the contents of which are incorporated by reference herein, back-side diamond thermal paths are provided effectively to act as cooling fins; or alternatively, front-side shallow trench diamond thermal conductors are provided in contact with the devices at the substrate surface and extend through the BOX layer to contact the underlying bulk silicon. The shallow trench diamond structures provide both electrical isolation between devices and thermal conduction of heat away from the devices. A disadvantage to the former Joshi structure is that back-side cooling does nothing for dissipating heat away from the front-side-mounted devices. A disadvantage to the latter Joshi front-side structure and method is that the trenches are formed prior to device fabrication. As a result, the diamond in the trenches must be recessed and covered to protect it from the subsequent processing steps; thereby requiring numerous additional processing steps and resulting in an unusual structural profile.
It is therefore an objective of the present invention to provide improved cooling through thermal conduction structures for semiconductor devices.
It is additionally an objective of the invention to provide a method for creating thermal conduction paths for SOI devices on the front side of the wafer.
Yet another objective of the invention is to provide a method for incorporating thermal conduction paths into SOI structures which is compatible with currently-used SOI fabrication processes.